The wide spread use of integrated circuits (ICs), also referred to as "chips", in numerous applications is well known. Typically, in the manufacture of integrated circuits, a semiconductor wafer is formed having regions of insulating, conductive and semiconductive materials. For example, semiconductive regions or conductive metal regions can be formed in trenches of a silicon substrate.
As a result of the ever increasing number of uses for integrated circuits, manufacturing these devices has become increasingly competitive. Accordingly, the focus on development has been to increase chip performance while decreasing production cost.
Current trends in the integrated circuit industry include fabricating smaller devices having increased chip density. Reducing chip size can reduce chip manufacturing costs. In addition, devices having smaller dimensions can be advantageous because device delay can also be decreased, thereby increasing performance.
Device performance can also be increased by adding multiple levels of metallization. More particularly, the use of multiple levels of metal interconnections allows for wider interconnect layer dimensions with shorter interconnect lengths. Because such lengths have only been possible with single level devices, a corresponding decrease in interconnect delay has been achieved. Nonetheless, as many interconnect levels are added, topography that builds up with each level can become severe. Consequently, the reliability associated with fabricating a device including several thin layers can be sensitive.
To reduce the topography, interconnect levels are typically planarized. As known in the art, planarization may be described in three degrees including: (1) surface smoothing in which feature corners are smoothed and high aspect ratio holes are filled; (2) local-planarity whereby surfaces are flat locally but surface height varies across the die; and (3) global planarity where the surface is flat across the entire area.
As circuit dimensions are reduced, interconnect levels must be globally planarized to produce a reliable, high density device. Chemical mechanical polishing (CMP) is gaining rapid acceptance as the technique of choice for globally planarizing interlevel dielectric (ILD) layer surfaces and for delineating metal patterns in integrated circuits. F. B. Kaufman, et al., J. Electrochem. Soc. 138, 3460 (1991); C. W. Kaanta, et al., in IEEE Proc. Multilevel Interconnect Conf., p. 144, (Santa Clara, Calif. June 1991).
In general, CMP processes involve holding or rotating a semiconductor wafer against a rotating wetted polishing surface under a controlled downward pressure. A chemical slurry containing a polishing agent, such as alumina or silica, is typically used as the abrasive medium. Additionally, the chemical slurry can contain chemical etchants for etching various surfaces of the wafer. In a typical fabrication of a device, CMP is first employed to globally planarize an ILD layer surface comprising only dielectric. Trenches and vias are subsequently formed and filled with metal by known deposition techniques. CMP is then typically used to delineate a metal pattern by removing excess metal from the ILD.
CMP is advantageous because it can be performed in one step, in contrast to past planarization techniques which are complex, involving multiple steps. Moreover, CMP has been demonstrated to maintain high material removal rates at high surface features and low removal rates at low features, thus allowing for uniform planarization. CMP can also be used to remove different layers of material and various surface defects. CMP thus can improve the quality and reliability of the ICs formed on the wafer.
A particular problem encountered during CMP processing, however, is the control of the various processing parameters to achieve the desired wafer characteristics. For example, in removing or planarizing a metal layer, it can be necessary to remove the metal to the top of the underlying layer without removing any portion thereof, i.e., overcut, yet also to achieve global planarization, i.e., avoid undercutting, as described above. Thus, to utilize CMP, an end point detector for the process is necessary.
Various techniques have been investigated for detecting the end point of CMP processes. For example, U.S. Pat. No. 5,217,586 to Datta et al. describes end point detection techniques involving coulometry or by tailoring the bath chemistry. U.S. Pat. No. 5,196,353 to Sandhu et al. describes end point detection using surface temperature measurements. U.S. Pat. No. 5,245,794 to Salugsugan describes an audio end point detector. U.S. Pat. No. 5,240,522 to Yu et al. describes an end point detector which detects reflected acoustic waves. U.S. Pat. No. 5,242,524 to Leach et al. describes an end point detector using impedance detection.
Despite these and other techniques for detecting the end point of a CMP process, it would be advantageous to provide an effective CMP system and process for globally planarizing and delineating layers in a semiconductor device, and particularly metal layers in multilevel semiconductor devices. It would further be advantageous to provide a CMP system and process having an effective end point detector to monitor and signal the end of the polishing process, i.e., when metal is completely removed from above an ILD surface, leaving metal only in the trenches and vias. In addition, it would be advantageous to provide a CMP system and process for detecting the end point during the CMP process, without having to remove the wafer from the system to determine if an end point has been reached.